1. Field of the Invention
The present invention relates to a display device for performing display data reading and writing operations during a specified display period.
2. Description of the Prior Art
FIG. 7 is a block diagram showing a conventional display device. As shown in FIG. 7, the display device consists of a CPU 1, a display control unit 2, a pixel information recording DRAMs 31, 32 and a display unit 4.
The CPU 1 applies 16 bit system address SA for specifying a writing address to the DRAM 31, 32 and 8-bit system data SD for specifying writing data to the dislay control unit 2.
The system address SA is taken in at an A-input of a selector 11 within the display control unit 2. The selector 11 takes in 16-bit display address DA generated by a display address generator 10 at its B-input, and then, in accordance with a selection signal S12 received from the timing generator 12 to a control input S, applies one of the system address SA and display address DA as an inside address MA by 8 bits (in order of the most significant 8 bits followed by the least significant 8 bits) to address inputs A of the DRAMs 31, 32, respectively.
Beside the above mentioned selective signal 12, the timing generator 12 synchronizes a clock CLK received from the outside to apply a timing signal T1 to a T-input of a serial/parallel converter 15 and a timing signal T2 to a T-input of a holding circuit 14 (consisting of circuits 14a and 14b). The timing generator 12 also applies control signal SC consisting of a row address strobe signal RAS, a column address strobe signal CAS and a writing control signal WE to control inputs C of the DRAMs 31, 32, respectively, and the writing control signal WE to a buffer 13.
The buffer 13 is activated when the writing control signal WE turns to Low, and applies the system data SD as the inside data MD; the least significant 4 bits to a data input/output D of the DRAM 31 and the most significant 4 bits to a data input/output D of the DRAM 32, respectively.
The holding circuits 14a, 14b receive 4-bit data d1, d2 from the data inputs/outputs D of the DRAMs 31, 32 and take them in as 4-bit latch data at a control timing of the timing signal T2 to apply the 4-bit latch data from Q-outputs to a D-input of the serial/parallel converter 15.
The serial/parallel converter 15 takes in the two 4-bit latch data from the holding circuits 14a, 14b at a control timing of the timing signal T1 to apply them as 8-bit display data VD from its Q-output to the display unit 4.
The DRAMs 31, 32 store the inside data MD taken in from the data inputs/outputs D as writing data in addresses specified by the inside address MA upon writing, under the control of the control signal SC taken in the control inputs C to apply the data stored in the address specified by the inside address MA upon writing from the data inputs/outputs D.
FIG. 8 is a timing chart showing the reading and writing operations of display data in the display device shown in FIG. 7. Now, the display data writing operation will be described with reference to FIG. 8.
First, the system address SA from the CPU1 is taken in from the A-input of the selector 11. At this time, the selector 11 is set so as to apply the A-input as the inside address MA in accordance with an instruction of the selection signal S12. Thus, the system address SA is output in order of the most significant eight bits followed by the least significant eight bets as the inside address MA.
In accordance with the falling of a row address strobe signal RAS, a row address RA (the most significant 8 bits of the system address SA) as the inside address MA is applied commonly to the address inputs A of the DRAM 31, 32. Then, after the writing control signal WE is set to Low, with the successive falling of the column address strobe signal CAS, a column address CA (the least significant 8 bits of the system address SA) as the inside address MA is applied commonly to the address inputs A of the DRAMs 31, 32 to set writing addresss to the DRAMs 31, 32.
At the same time, since the writing control signal WE is Low and the buffer 13 is activated, system data SD are applied as the inside data MD from the buffer 13 to the data inputs/outputs D of the DRAMs 31, 32. Specifically, the most significant 4 bits of the inside data MD are applied to the data input/output D of the DRAM 32 while the least significant 4 bits are applied to the data input/output D of the DRAM 31.
With the above-mentioned operation, the data specified by the system data SD are written in the addresses of the DRAMs 31, 32 specified by the system address SA.
FIG. 9 is a diagram showing an address arrangement in the DRAMs 31, 32. As shown in FIG. 9, each of the DRAMs 31, 32 has an address space of 64K.times.4 (bits); the DRAM 31 stores the least significant 4-bit data of the display data in its addresses 0000 h to FFFFh while the DRAM 32 stores the most significant 4-bit data of the display data in its addresses 0000 h to FFFFh. Thus, a single attempt of the above mentioned writing operation allows the display data to be written in one address in each of the DRAMs 31, 32.
Next, the display data reading operation will be described. During the display data reading operation, the display address generator 10 applies the display address DA to the B-input of the selector 11, incrementing address by address from a start address 0000 h. At this time, the selector 11 is set so that it may output the B-input as the inside address MA according to an instruction of the selection signal S12. Thus, the display address DA is applied in order of the most significant 8 bits followed by the least significant 8 bits as the inside address MA to the address inputs A of the DRAMs 31, 32. The writing control signal WE during the display operation is fixed in High (shown by a broken line in FIG. 8).
With the falling of the row address strobe signal RAS, the row address RA (the most significant 8 bits of the display address DA) as the inside address MA is applied commonly to the address inputs A of the DRAMs 31, 32. Then, with the falling of the column address strobe signal CAS, the column address CA (the least significant 8 bits of the display address DA) as the inside address MA is applied commonly to the address inputs A of the DRAMs 31, 32.
Then, in accordance with the control signal SC from the timing generator 12, the DRAMs 31, 32 apply the 4-bit data d1, d2, or the data stored in the addresses specified by the inside address MA, from the date inputs/outputs D. Then, the holding circuits 14a, 14b take in the 4-bit data d1, d2 as 4-bit latch data at a timing specified by the timing signal T2 of the timing generator 12.
After that, according to an instruction of the timing signal T1 from the timing generator 12, the serial/parallel converter 15 takes in the 4-bit latch data obtained from the Q-outputs of the holding circuits 14a, 14b at its D-input and applies 8-bit display data VD from its Q-output to the display unit 4. The above statement is about the display data reading operation, and successively, the display unit 4 displays an image in accordance with the display data VD.
After that, a display address generator 10 alters the display address DA by incrementing one by one to perform the above mentioned display data reading operation and image display operation to all the addresses of which a picture is made up, so that a picture of display data are displayed on the display unit 4. Thereafter, the display unit 4 always displays the same picture unless the data stored in the DRAMs are renewed.
To change the picture contents displayed on a screen of the display unit 4, naturally it is necessary to renew the data stored in the DRAMs 31, 32. As shown in FIG. 10, the renewal of the data stored in the DRAMs 31, 32 are carried out by an interruption of a display data reading cycle and display writing cycle together during a display period.
In an example shown in FIG. 10, the interruption of the display data writing cycle is performed once per seven times of display data reading cycles 1 to 7 during the display period when the display data presents 7 bytes (8 bits.times.7=56) pixels. The reason why the display period can be interrupted by the display data writing cycle is that a time required for the image display on the display unit 4 is longer than the display data reading period upon the display of a specified number (e.g., 1 byte) of pixels. Thus, by virtue of a difference in time between 1-bite display period and 1-bite display data reading time calculated in accordance with a required timing of the DRAMs, the interruption of the display data writing cycle once per specified cycles (7 cycles in the example shown in FIG. 10) is possible.
In the conventional display device structured as mentioned above, a display data writing cycle is set once per a specified number of display data reading cycles during a specified display period. In such a conventional method, however, a time required for a display data reading cycle is not adequately short, and there is not a sufficient time for an interruption of a display data renewal cycle during the specified display period. Accordingly, there arises the problem that a time required for the display data renewal is too long during the display period.